It is known in the art that a transistor subjected to different types of stress increases the mobility of the charge carriers in the channel region. For example, creating a tensile stress in the channel region increases the mobility of electrons and, depending on the magnitude of the stress, increases in mobility of up to 20% may be obtained. This, in turn, directly translates into an increase in conductivity and faster speed. Similarly, compressive stress in the channel region may increase the mobility of holes, thereby providing enhanced performance of those transistors which conduct based on the mobility of holes.
Consequently, it has been proposed to introduce a compressive stress into the channel region of P-type transistors and a tensile stress into the channel region of N-type transistors. A number of structures have been proposed in the prior art to induce stress in these respective channel regions.
FIG. 1 illustrates a structure commonly used in the prior art for inducing stress in the channel regions of transistors. This structure includes a plurality of transistors 1 having a shallow trench isolation region 2 formed therebetween. Each of the transistors includes a respective gate dielectric 3 and a gate electrode 4. Positioned underneath the gate electrode 4 is a channel region 5. Adjacent the channel region 5 is a source/drain region 6 that is positioned in the substrate between the trench isolation region 2 and the channel region 5. Sidewall spacers 7 and a silicide layer 8 are also formed as is known in the art.
A dielectric layer 9, which is compressively stressed, is then deposited overlying the semiconductor integrated circuit structure, including the transistors 1, the source/drain regions 6, and the trench isolation region 2. For an N-type transistor, the dielectric layer 9 is a silicon nitride layer having a specified compressive stress. The dielectric layer 9 can be deposited having the desired magnitude of compressive stress or tensile stress as is known in the art in order to achieve the stress characteristics needed within the dielectric layer 9.
A structure of the type shown in FIG. 1 is described and shown in detail in U.S. Patent Application Publication No. 2005/0263825 to Fulmberg et al., (the '825 application) which is incorporated herein by reference.
While the structure of FIG. 1 illustrates an attempt for inducing stress into the channel of the transistor, it has the shortcoming that the stress is only indirectly applied to the channel region and is difficult to precisely apply to the channel region.
Another technique for forming a strained channel region is shown in U.S. Pat. No. 7,221,024, but this involves a number of difficult process steps and many additional masks.